česky english Vítejte, dnes je úterý 12. prosinec 2017 Přihlásit E-archiv Speciály Ukázkové číslo Předplatné Kontakt

Webináře živě

Importance of Optimizing Via Designs for Signal Integrity

Mentor, a Siemens business

In this webinar, you will learn why accurate via modeling is important for your designs depending on the data rate. We will show you different via modeling methods in HyperLynx®. Techniques to improve both single-ended and differential via designs will also be discussed.

Datum: 12. 12. 2017 - 18:00 SEČ (60 minut)
Date: December 12th, 2017 - 09:00 AM US/Pacific | 18:00 CET (60 minutes)

 

Practical Tips to Help You Achieve Industry 4.0 Benefits

AEGIS

Changing customer expectations are forcing manufacturers to rethink their operations in order to innovate faster, and bring connected products to the connected customer. As customers have more choices than ever before and competition is increasing globally, manufacturers need to adapt quickly to dramatically shorten time-to-market and maximize productivity, ultimately exceeding customer expectations.

Datum: 12. 12. 2017 - 19:00 CET (60 minut)
Date: Dec 12, 2017 - 1:00pm EST | 12:00pm CST | 10:00am PST | 18:00 UTC | 7:00 PM CET (60 minutes)

 

C++ for the Embedded Developer

Mentor, a Siemens business

The C++ language has become more popular for embedded development in recent years. We will look at the features of the language that make it especially attractive and appropriate for such applications.

Datum: 20. 12. 2017 - 19:00 SEČ (60 minut)
Date: December 20th, 2017 - 10:00 AM US/Pacific | 19:00 CET (60 minutes)

 

A Strategy for C to C++ Migration

Mentor, a Siemens business

Most embedded developers, who start to use C++ (or plan to do so), are currently using C. They need to migrate their expertise and any existing code to the new language. We will look at a three-stage strategy for making this migration.

Datum: 17. 1. 2018 - 19:00 SEČ (60 minut)
Date: January 17th, 2018 - 10:00 AM US/Pacific | 19:00 CET (60 minutes)

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